library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity demux is
port (
		out0 : out std_logic_vector(7 downto 0);   --output bit
		out1 : out std_logic_vector(7 downto 0);   --output bit
		out2 : out std_logic_vector(7 downto 0);   --output bit
		out3 : out std_logic_vector(7 downto 0);   --output bit
		ACK0 : out std_logic;
		ACK1 : out std_logic;
		ACK2 : out std_logic;
		ACK3 : out std_logic;
		sel  : in std_logic_vector(2 downto 0);
        selReady : IN STD_LOGIC;
        spaceValid: IN STD_LOGIC;
		busIn : in std_logic_vector(7 downto 0)   --input bit
     );
end demux;

architecture Behavioral of demux is

begin
process(busIn,sel)
begin
	IF(selReady = '1' AND spaceValid='1') THEN
		case sel is
		  when "000" => out0 <= busIn; out1 <= "00000000"; out2 <= "00000000"; out3 <="00000000";
			ACK0<='1'; ACK1<='0'; ACK2<='0'; ACK3<='0';
		  when "001" => out1 <= busIn; out0 <= "00000000"; out2 <= "00000000"; out3 <="00000000";
			ACK1<='1'; ACK0<='0'; ACK2<='0'; ACK3<='0';
		  when "010" => out2 <= busIn; out0 <= "00000000"; out1 <= "00000000"; out3 <="00000000";
			ACK2<='1'; ACK0<='0'; ACK1<='0'; ACK3<='0';
		  when "011" => out3 <= busIn;  out0 <= "00000000"; out1 <= "00000000"; out2 <="00000000"; 
			ACK3<='1'; ACK0<='0'; ACK1<='0'; ACK2<='0';
		  when others => out0 <= busIn;  out1 <= busIn; out2 <= busIn; out3 <=busIn; 
			ACK0<='1'; ACK1<='1'; ACK2<='1'; ACK3<='1';
		end case; 
	
	ELSE 
		out0 <= "00000000"; out1 <= "00000000"; out2 <= "00000000"; out3 <="00000000";
		ACK0<='0'; ACK1<='0'; ACK2<='0'; ACK3<='0';
	END IF;
end process;

end Behavioral;